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STA559BWQS
5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD(R)
Features
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Wide supply voltage range (4.5 - 9 V) 3 Power output configurations: - 2 channels of ternary PWM (stereo mode) (2 x 3 W) into 4 at 5 V - 3 channels - left,right using binary and LFE using ternary PWM (2.1 mode) (2 x 0.7 W + 1 x 3 W) into 4 at 5 V (2 x 1.4 W + 1 x 6 W) into 2 at 5 V - 2 channels of ternary PWM (2 x 3 W) + PWM driver for SW 2.1 channels of 24-bit DDX(R) 100-dB SNR and dynamic range Selectable 32 kHz to 192 kHz input sample rates I2C control with selectable device address Digital gain/attenuation +48 dB to -80 dB in 0.5-dB steps Soft volume update Individual channel and master gain/attenuation Dual independent limiters/compressors Dynamic range compression or anti-clipping modes AutoModes - 15 preset crossover filters - 2 preset anti-clipping modes - Preset night-time listening mode Individual channel and master soft and hard mute Independent channel volume and DSP bypass
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PowerSSO-36 slug down
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Automatic zero-detect mute Automatic invalid input detect mute 2-channel I2S input data interface Input and output channel mapping 4 28-bit user programmable biquads (EQ) per channel DC blocking selectable high-pass filter Selectable de-emphasis Sub channel mix into left and right channels Advanced AM interference frequency switching and noise-suppression modes Selectable high or low bandwidth noise-shaping topologies Variable max power correction for lower full-power THD Thermal overload and short-circuit protection Video application supports 576 x fs input mode QSound QHD(R) - Field proven stereo soundfield enhancement technology - Provides improved audio image width, seperation and depth for stereo signals - Synthesizes a 3-D stereo soundfield PowerSSO-36 slug down package
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Table 1. Order codes
Part number STA559BWQS STA559BWQS13TR Temp range, C 0 to 150 0 to 150 Package PowerSSO-36 slug down PowerSSO-36 slug down Tube Tape&Reel Packing
March 2008
Rev 1
1/66
www.st.com 1
Contents
STA559BWQS
Contents
1 Description and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 1.2 1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 QSound QHD(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Connections diagram and pins description . . . . . . . . . . . . . . . . . . . . . 12
2.1 2.2 2.3 Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 3.3 3.4 3.5 3.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical specifications - power Section . . . . . . . . . . . . . . . . . . . . . . . . . 16 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.1 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1 4.1.2 4.1.3 4.1.4 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 4.3
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1 4.3.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.1 4.4.2 4.4.3 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/66
STA559BWQS 4.4.4 4.4.5 4.4.6
Contents Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1 5.3.2 5.3.3 DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DDX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 33 Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 34
5.4
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 36 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MiamiMode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 38
3/66
Contents 5.5.7 5.5.8
STA559BWQS Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 41 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 42
5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Channel 3/line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8
Auto mode registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . 44
5.8.1 5.8.2 5.8.3 5.8.4 AutoMode register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AutoMode register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.9
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 46
5.9.1 5.9.2 5.9.3 5.9.4 5.9.5 5.9.6 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.10 5.11
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dynamics control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 48
5.11.1 5.11.2 5.11.3 5.11.4 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.12
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 51
4/66
STA559BWQS 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.12.8 5.12.9
Contents Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b1data register bits 23..16 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Coefficient b1data register bits 15..8 address . . . . . . . . . . . . . . . . . . . . 52 Coefficient b1data register bits 7..0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Coefficient b2 data register bits 23..16 . . . . . . . . . . . . . . . . . . . . . . . . . 52 Coefficient b2 data register bits 15..8 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Coefficient b2 data register bits 7..0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Coefficient a1 data register bits 23..16 . . . . . . . . . . . . . . . . . . . . . . . . . 52 Coefficient a1 data register bits 15..8 . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.12.10 Coefficient a1 data register bits 7..0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.11 Coefficient a2 data register bits 23..16 . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.12 Coefficient a2 data register bits 15..8 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.13 Coefficient a2 data register bits 7..0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.14 Coefficient b0 data register bits 23..16 . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.15 Coefficient b0 data register bits 15..8 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.16 Coefficient b0 Data Register Bits 7..0 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.12.21 Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.13 5.14 5.15 5.16
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 58 Variable distortion compensation registers (addr 0x29-0x2A) . . . . . . . . . 58 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 58 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 6.2 6.3 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 8 9
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 License information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5/66
Contents
STA559BWQS
10 11
Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 64 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6/66
STA559BWQS Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical specifications - power Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Input sample rates and clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Support serial audio input formats for MSB-First (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . 30 Supported serial audio input formats for LSB-First (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 31 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DXX power output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DXX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MiamiMode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7/66
STA559BWQS Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AutoMode gain compression/limiters selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AutoMode AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter attack rate as a function of LxA bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Limiter release rate as a function of LxR bits.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Limiter attack threshold as a function of LxAT bits (AC-Mode). . . . . . . . . . . . . . . . . . . . . . 50 Limiter release threshold as a function of LxRT bits (AC-Mode) . . . . . . . . . . . . . . . . . . . . 50 Limiter attack threshold as a function of LxAT bits (DRC-mode). . . . . . . . . . . . . . . . . . . . . 51 Limiter release threshold as a as a function of LxRT bits (DRC-mode).. . . . . . . . . . . . . . . 51 RAM block for biquads, mixing, scaling, and bass management . . . . . . . . . . . . . . . . . . . . 57 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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STA559BWQS Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output power vs supply voltage (RL = 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output power vs. supply voltage (RL = 8 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output power vs. supply voltage (RL = 8 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Efficiency vs. Pout (Vcc = 9 V; RL = 8 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Efficiency vs. Pout (Vcc = 5 V; RL = 4 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Efficiency vs. Pout (Vcc = 5 V; RL = 2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PSSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Channel separation stereo DDX mode (RL = 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Channel separation stereo S.E. mode (RL = 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Channel separation stereo S.E. mode (RL = 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FFT 0 dBFS stereo DDX mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FFT -60 dBFS stereo DDX mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FFT 0 dBFS stereo S.E. mode (RL = 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FFT -60 dBFS stereo S.E. mode (RL = 4 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FFT 0 dBFS stereo S.E. mode (RL = 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FFT -60 dBFS stereo S.E. mode (RL = 2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Basic limiter and volume flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Double layer PCB with copper ground area and with 16 via holes . . . . . . . . . . . . . . . . . . 61 PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PowerSSO-36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 62
9/66
Description and block diagram
STA559BWQS
1
1.1
Description and block diagram
Description
The STA559BWQS is an integration of digital audio processing, digital amplifier control, DDX(R) power-output stage and QSound QHD(R) technology to create a high-power single-chip DDX solution with high-quality, high-efficiency and all digital amplification. The STA559BWQS power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 0.7 W + 1 x 3 W of power output. 2 channels can be provided by two full-bridges, providing up to 2x3W of power. The IC can also be configured as a 2.1 channels with 2 x 3 W provided by the device and external power for DDX(R) power drive. Also provided in the STA559BWQS are a full assortment of digital processing features. This includes up to 4 programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. AutoModes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions, for instance, auto volume loudness, preset volume curves and preset EQ settings. New advanced AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX(R) processing are provided. This high quality conversion from PCM audio to DDX patented 3-state PWM switching waveform provides over 100 dB of SNR and dynamic range.
1.2
QSound QHD(R)
Normally, reduced audio clarity is experienced due to the digital compression of music (and video-sound) combined with various audio processing techniques used in broadcast transmission. This is most apparent in products such as digital televisions and audio players. These devices are faced with a multitude of audio challenges, primarily associated with the small speakers, that are limited in location and cabinet housing, plus economized speaker drivers and components. As such digital televisions and audio players are ideal candidates to benefit from stereo soundfield enhancement in order to deliver a full surround-like experience. QSound QHD(R) and its industry recognized QXpander(R) technology is a field-proven stereo soundfield enhancement technology that provides a broader stereo image width with greater separation and depth for stereo signals and synthesizes a 3-D stereo soundfield. QHD(R) removes the small centralized audio sweet spot by creating a very wide stereo image with full immersive audio. QHD(R) and its QXpander(R) technology have been incorporated into hundreds of QSound and third party hardware and software products, with total shipments in the millions.
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STA559BWQS
Description and block diagram
1.3
Figure 1.
Block diagram
Block diagram
I2C I2S interface
Protection current/thermal Channel 1A
DSP (Equalization, Tone, Volume, Bass) DDX
Power control
Logic
Channel 1B
Channel 2A Regulators
PLL Bias
Channel 2B
Digital (DSP)
Power
11/66
Connections diagram and pins description
STA559BWQS
2
2.1
Connections diagram and pins description
Connections diagram
Figure 2. Pin connection PowerSSO-36 (top view)
GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD GND OUT3B/DDX3B OUT3A/DDX3A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD_DIG GND_DIG SCL SDA INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG TWARN/OUT4B EAPD/OUT4A
D05AU1638
2.2
Pins description
Table 2.
Pin 1 2 3 4 5 6 7 8 9
Pin description
Type GND I I I/O I/O O GND Power O Name GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A Substrate ground I2C select address This pin must be connected to ground Internal reference at Vcc - 3.3 V Internal Vcc reference Output half bridge 2B Power negative supply Power positive supply Output half bridge 2A Description
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STA559BWQS Table 2.
Pin 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Connections diagram and pins description Pin description (continued)
Type O Power GND I/O GND Power I/O O O O I Power GND I Power I GND I I I I I O I/O I GND Power Name OUT1B VCC1 GND1 OUT1A GND_REG VDD GND OUT3B/DDX3B OUT3A/DDX3A EAPD/OUT4A TWARN/OUT4B VDD_DIG GND_DIG PWRDN VDD_PLL FILTER_PLL GND_PLL XTI BICKI LRCKI SDI RESET INT_LINE SDA SCL GND_DIG VDD_DIG Description Output half bridge 1B Power positive supply Power negative supply Output half bridge 1A Internal ground reference Internal 3.3 V reference voltage Power negative supply PWM out CH3B - external bridge PWM out CH3A - external bridge Power down for external bridge Thermal warning from external bridge Digital supply voltage Digital ground Power down Positive supply for PLL Connection to PLL filter Negative supply for PLL PLL input clock I2S serial clock I2S left/right clock I2S serial data channels 1 and 2 Reset Fault interrupt I2C serial data I2C serial clock Digital ground Digital supply voltage
13/66
Connections diagram and pins description
STA559BWQS
2.3
Table 3.
Symbol Rth j-amb Tth-sdj Tth-w Tth-sdh
Thermal data
Thermal data
Parameter Thermal resistance junction-ambient PowerSSO-36 Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis temperature
(1)
Min
Typ 24 150 130 25
Max
Unit C/W C C C
1. See Chapter 7: Package thermal characteristics on page 61 for details.
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STA559BWQS
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol Vcc Vdd Top Tstg
Absolute maximum ratings
Parameter Power supply voltage (VCC1, VCC2) Logic supply Operating junction temperature Storage temperature -0.3 -20 -40 Min Typ Max 18 4 150 150 Unit V V C C
Note:
Stresses beyond those listed under "Absolute maximum ratings" make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended operating condition" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supply with nominal value rated inside recommended operating conditions, may experience some rising beyond the maximum operating condition for short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded.
3.2
Recommended operating condition
Table 5.
Symbol Vcc Vdd Tamb
Recommended operating condition
Parameter Power supply voltage (VCC1, VCC2) Logic supply Ambient temperature Min 5.0 2.7 -20 3.3 Typ Max 16.0 3.6 70 Unit V V C
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Electrical specifications
STA559BWQS
3.3
Table 6.
Symbol Iil Iih Vil Vih Vol Voh Ipu Rpu
Electrical specifications - digital section
Electrical specifications - digital section
Parameter Conditions -10 -10 Min Typ 10 10 Max Unit A A
Low level input current without pull device Vi = 0 V High level input current without pull device Low level input voltage High level input voltage Low level output voltage High level output voltage Pull current Equivalent pull resistance Iol = 2 mA Ioh = 2 mA Vi = VDD_DIG = 3.6 V
0.2 * VDD_DIG V 0.8 * VDD_DIG V 0.4 * VDD_DIG V 0.8 * VDD_DIG -25 66 50 125 V A k
3.4
Electrical specifications - power Section
The specifications given in this section are with the operating conditions VCC = 5 V, fsw = 384 kHz, Tamb = 25 C, RL = 4 unless otherwise specified.
Table 7.
Symbol RdsON Idss gP gN ILDT IHDT tr tf Vcc
Electrical specifications - power Section
Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage ldss Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current dead time (static) High current dead time (dynamic) Rise time Fall time Supply operating voltage Supply current from Vcc in power down Supply current from Vcc in 3-state Power Down = 0 TRISTATE = 0 PCM input signal = -60 dBFS Switching frequency = 384 kHz No LC filters 15 ld = 1 A Vcc = 9 V ld = 1 A ld = 1 A Resistive load(1) Iload = 2 A(2) Resistive load(1) Resistive load
(1)
Conditions
Min
Typ 180
Max 250 10
Unit m A % %
95 95 5 10 8 8 4.5 10 20 10 10 16 10
ns ns ns ns V A mA
Icc
Supply current from Vcc in operation
30
mA
Supply current DDX processing Internal clock = 49.152 MHz (reference only) on VDD_DIG
80
mA
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STA559BWQS Table 7.
Symbol Ilim Isc UVL tmin
Electrical specifications
Electrical specifications - power Section (continued)
Parameter Overcurrent limit Short circuit protection Under voltage protection threshold Output minimum pulse width Output power BTL Output power SE Output power BTL No Load THD = 1%, f = 1 kHz THD = 10%, f = 1 kHz THD = 1%, f = 1 kHz THD = 10%, f = 1 kHz RL = 8 Vcc = 9 V f = 1 kHz THD = 1% THD = 10% THD = 1% THD = 10% RL = 2 Vcc = 5 V f = 1 kHz THD = 1% THD = 10% THD = 1% THD = 10% 20 Conditions Min 2.2 2.7 Typ 3.0 3.6 3.5 30 2.3 3 0.5 0.7 4.2 5.3 0.9 1.2 4.2 5.3 1 1.3 100 A-weighted 90 Stereo DDX mode, <5 kHz VRIPPLE = 1 V RMS Audio input = dither only DDX stereo mode, Po = 1 W, f = 1 kHz Stereo DDX mode, <5 kHz One channel driven @ 1 W Other channel measured Po = 2 x 3 W, 4 Po = 2 x 0.7 W + 1 x 3 W, 4 80 dB 4.3 60 Max Unit A A V ns W W W W W W dB
Po Output power SE Output power BTL Output power SE Signal to noise ratio, ternary mode Signal to noise ratio binary mode Power Supply Rejection Ratio Total harmonic distortion + noise Crosstalk Peak efficiency, DDX mode Peak efficiency, Binary modes
SNR
PSSR
THD+N
0.2
%
XTALK
80 90 87
dB
%
1. Refer to Test Circuit 1 Figure 3 2. Refer to Test Circuit 2 Figure 4
17/66
Electrical specifications
STA559BWQS
3.5
3.5.1
Testing
Functional pin status
Table 8.
Pin name PWRDN PWRDN TWARN TWARN EAPD EAPD 23 23 20 20 19 19
Functional pin status
Pin # Logic value 0 1 0 1 0 1 Low absorption Normal operation From external power stage is indicated a temperature warning. Normal operation Low absorption for power stage. All internal regulators are switched off. Normal operation IC status
Figure 3.
Test circuit 1
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 4.
Test circuit 2
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC
Duty cycle=A
DTout(A) M58 Q1 OUTA Rload=4 L67 10 C69 470nF DTout(B) L68 10 C70 470nF Q2 OUTB M64
Duty cycle=B
DTin(A) INA
DTin(B) INB
Iout=1A M57 Q3
Iout=1A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D06AU1649
18/66
STA559BWQS
Electrical specifications
3.6
Figure 5.
Electrical characteristics curves
Output power vs supply voltage (RL Figure 6. = 2 )
Po(W) 10 9
Output power vs. supply voltage (RL = 2 )
Po(W) 3
2.5
Rload = 2 f = 1KHz
8 7
THD=10%
Rload = 2 f = 1KHz BTL THD=10 %
2
S.E.
6 5 4
1.5
1 THD=1% 500m
3 2 1
THD=1%
0 +4.5 +4.6 +4.7 +4.8 +4.9
+5
+5.1 +5.2 +5.3 +5.4 +5.5 +5.6 +5.7 +5.8 +5.9 +6 Vcc(V)
0 +4.5 +4.6 +4.7 +4.8 +4.9
+5
+5.1 +5.2 +5.3 +5.4 +5.5 +5.6 +5.7 +5.8 +5.9 +6 Vcc (V)
Figure 7.
Output power vs. supply voltage (RL Figure 8. = 4 )
Po(W) 12 11
Output power vs. supply voltage (RL = 4 )
Po(W) 3 2.5 2 1.5 THD=1% 1 500m
Rload = 4 f = 1KHz S.E. THD=10%
10 9 8 7 6 THD=1% 5 4 3 2 Rload = 4 f = 1KHz BTL THD=10%
0 +4.5
+5
+5.5
+6
+6.5
+7
+7.5
+8
+8.5
+9
+9.5 +10
1 0 +4.5 +5 +5.5 +6 +6.5 +7 +7.5 Vcc(V) +8 +8.5 +9 +9.5 +10
Vcc (V)
Figure 9.
Output power vs. supply voltage (RL Figure 10. Output power vs. supply voltage (RL = 6 ) = 6 )
Po(W) 10 9 8 7
Rload = 6 f = 1KHz S.E. THD=1% THD=10%
Po(W)
3
2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 +4.5 +5 +5.5 +6 +6.5 +7 +7.5 +8 +8.5 +9 +9.5 +10
Rload = 6 f = 1KHz BTL THD=1% THD=10%
6 5 4 3 2 1 0 +4.5 +5
+5.5
+6
+6.5
+7
+7.5
+8
+8.5
+9
+9.5 +10
Vcc(V)
Vcc(V)
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Electrical specifications
STA559BWQS
Figure 11. Output power vs. supply voltage (RL Figure 12. Output power vs. supply voltage (RL = 8 ) = 8 )
Po(W) 3
Po(W)10 9 8 7
Rload = 8 f = 1KHz SE THD=10%
2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 THD=1%
6 Rload = 8 5 4 3 THD=1% 2 1 f = 1KHz BTL THD=10%
0 +4.5
+5
+5.5
+6
+6.5
+7
+7.5
+8
+8.5
+9
+9.5 +10
Vcc(V)
0 +4.5
+5
+5.5
+6
+6.5
+7 +7.5 Vcc(V)
+8
+8.5
+9
+9.5 +10
Figure 13. Efficiency vs. Pout (Vcc = 9 V; RL = 8 )
100 90 80 70 60 Eff (%) 50 40 30 20 10 0 1 2 3 2xPout (W) 4 5 6 Vcc= 9V Rload= 8 f = 1KHz BTL
Figure 14. Efficiency vs. Pout (Vcc = 5 V; RL = 4 )
100 90 80 70 60 Eff(%) 50 40 30 20 10 0 500m 1 1.5 2xPout (W) 2 2.5 3 Vcc = 5V Rload = 4 f = 1KHz BTL
Figure 15. Efficiency vs. Pout (Vcc = 5 V; RL = 2 )
100 90 80 70 60 Eff(%) 50 40 30 20 10 0 500m 1 1.5 2 2.5 2 x Pout (W) 3 3.5 4 Vcc = 5V R load = 2 f = 1KHz BTL
Figure 16. THD vs. frequency
THD% 1 0.5
0.2 Stereo DDX Mode 0.1 Vcc=5V, Po= 1W
8ohm 4ohm 6ohm
0.05
0.02 0.01 20
50
100
200
500 Freq(Hz)
1k
2k
5k
10k
20k
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STA559BWQS
Electrical specifications
Figure 17. PSSR
Figure 18. Channel separation stereo DDX mode (RL = 2 )
T
dBr +10 +0
dBr +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 30 40 50 60 70 80 90 100 Frequency Hz 6ohm 8ohm Vcc = 5V Po = 1W
-10 -20 -30 -40 -50 -60 -70 Stereo DDX Mode Vcc= 5v, Rl=4 Po = 1W
4ohm
-80 -90
200
-100 20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 19. Channel separation stereo S.E. mode (RL = 2 )
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k Frequency (Hz) 2k 5k 10k 20k Stereo S.E. Mode Rl = 2,Vcc=5V Po = 1W
Figure 20. Channel separation stereo S.E. mode (RL = 4 )
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k Stereo S.E. Mode Rl = 4,Vcc=5V Po = 1W
Frequency (Hz)
Figure 21. FFT 0 dBFS stereo DDX mode
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20
Figure 22. FFT -60 dBFS stereo DDX mode
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20
Stereo DDX Mode Vcc=5V, Rl=4 f = 1KHz
Stereo DDX Mode Vcc=5V, Rl=4 f = 1KHz
50
100
200
500
1k
2k
5k
10k
20k
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
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Electrical specifications
STA559BWQS
Figure 23. FFT 0 dBFS stereo S.E. mode (RL = 4 )
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 Stereo S.E. Mode Vcc=5V, Rl=4 f = 1KHz
Figure 24. FFT -60 dBFS stereo S.E. mode (RL = 4 )
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 Stereo S.E. Mode Vcc=5V, Rl=4 f = 1KHz
50
100
200
500
1k
2k
5k
10k
20k
-130
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
Figure 25. FFT 0 dBFS stereo S.E. mode (RL = 2 )
dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz)
Figure 26. FFT -60 dBFS stereo S.E. mode (RL = 2 )
dBr A +10 +0 -10
Stereo S.E. Mode Vcc=5V, Rl=2 f = 1KHz
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20
Stereo S.E. Mode Vcc=5V, Rl=2 f = 1KHz
50
100
200
500 Frequency (Hz)
1k
2k
5k
10k
20k
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STA559BWQS
I2C bus specification
4
I2C bus specification
The STA559BWQS supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. STA559BWQS is always a slave device in all of its communications. It supports up to 400 kb/s rate (fast-mode bit rate). STA559BWQS I2C is a slave only interface.
4.1
4.1.1
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.
4.1.2
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
4.1.3
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA559BWQS and the bus master.
4.1.4
Data input
During the data input the STA559BWQS samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
4.2
Device addressing
To start communication between the master and the STA559BWQS, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA559BWQS the I2C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA559BWQS identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
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I2C bus specification
STA559BWQS
4.3
Write operation
Following the START condition the master sends a device select code with the RW bit set to 0. The STA559BWQS acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA559BWQS again responds with an acknowledgement.
4.3.1
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the STA559BWQS. The master then terminates the transfer by generating a STOP condition.
4.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.
4.4
4.4.1
Read operation
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA559BWQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
4.4.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA559BWQS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
4.4.3
Random address byte read
Following the START condition the master sends a device select code with the RW bit set to 0. The STA559BWQS acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA559BWQS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA559BWQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
4.4.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the STA559BWQS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
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STA559BWQS
I2C bus specification
4.4.5
Write mode sequence
Figure 27. Write mode sequence
ACK BYTE WRITE START DEV-ADDR RW ACK MULTIBYTE WRITE START DEV-ADDR RW SUB-ADDR ACK DATA IN ACK DATA IN STOP SUB-ADDR ACK DATA IN STOP ACK ACK
4.4.6
Read mode sequence
Figure 28. Read mode sequence
ACK CURRENT ADDRESS READ START NO ACK DEV-ADDR RW ACK RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START ACK SEQUENTIAL RANDOM READ START DEV-ADDR RW SUB-ADDR START ACK DEV-ADDR RW ACK DATA ACK DATA DEV-ADDR SUB-ADDR ACK DEV-ADDR DATA STOP ACK DATA NO ACK
RW RW= ACK HIGH DEV-ADDR DATA
START ACK DATA
RW ACK DATA NO ACK
STOP
STOP ACK DATA ST NO ACK
25/66
Register description
STA559BWQS
5
Table 9.
Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
Register description
Register summary
Name ConfA ConfB ConfC ConfD ConfE ConfF Mute/LOC Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 A1cf2 A1cf3 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C3B15 C3B7 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C3B14 C3B6 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C3B13 C3B5 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 C3B12 C3B4 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 C3B11 C3B3 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 C3B10 C3B2 BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 C3B9 C3B1 BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 C3B8 C3B0 C1EQBP C2EQBP C1TCB C2TCB XO3 XO2 D7 FDRB C2IM OCRB MME SVE EAPD LOC1 MV7 C1V7 C2V7 C3V7 ZDE ZCE PWDN LOC0 MV6 C1V6 C2V6 C3V6 MV5 C1V5 C2V5 C3V5 AMGC1 XO1 MV4 C1V4 C2V4 C3V4 AMGC0 XO0 AMAM2 AMAM1 AMAM0 AMAME D6 TWAB C1IM D5 TWRB DSCKE CSZ3 DRC DCCV ECLE D4 IR1 SAIFB CSZ2 BQL PWMS LDTE D3 IR0 SAI3 CSZ1 PSL AME BCLE C3M MV3 C1V3 C2V3 C3V3 D2 MCS2 SAI2 CSZ0 DSPB NSBW IDE C2M MV2 C1V2 C2V2 C3V2 D1 MCS1 SAI1 OM1 DEMP MPC OCFG1 C1M MV1 C1V1 C2V1 C3V1 D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV0 C1V0 C2V0 C3V0
26/66
STA559BWQS Table 9.
Addr 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30
Register description
Register summary (continued)
Name A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 DCC1 DCC2 FDRC1 FDRC2 Status reserved reserved reserved MPCC15 MPCC14 MPCC7 DCC15 DCC7 FDRC15 FDRC7 PLLUL MPCC6 DCC14 DCC6 FDRC14 FDRC6 FAULT MPCC13 MPCC5 DCC13 DCC5 FDRC13 FDRC5 UVFAULT RO1BACT R01BEND MPCC12 MPCC4 DCC12 DCC4 FDRC12 FDRC4 OVFAULT R5BACT R5BEND R5BBAD D7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 D6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 D5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 D4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 D3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 RA MPCC11 MPCC3 DCC11 DCC3 FDRC11 FDRC3 D2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 R1 MPCC10 MPCC2 DCC10 DCC2 FDRC10 FDRC2 D1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA MPCC9 MPCC1 DCC9 DCC1 FDRC9 FDRC1 TFAULT R2BACT D0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 DCC8 DCC0 FDRC8 FDRC0 TWARN R1BACT
OCFAULT OCWARN R4BACT R4BEND R4BBAD R3BACT R3BEND R3BBAD
R2BEND R1BEND R2BBAD R1BBAD
5.1
Configuration register A (addr 0x00)
D7 FDRB 0 D6 TWAB 1 D5 TWRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1
5.1.1
Master clock select
Table 10.
Bit 0 1 2
Master clock select
RW RW RW RW RST 1 1 0 Name MCS0 MCS1 MCS2 Master clock select: selects the ratio between the input I2S sample frequency and the input clock. Description
The STA559BWQS will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock will be:
" " "
32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48Z kHz, 96 kHz, and 192 kHz
27/66
Register description
STA559BWQS
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency, fs. The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally Table 11. Input sample rates and clock select
IR 101 32, 44.1, 48 88.2, 96 176.4, 192 00 01 1X 576 fs NA NA 100 128 fs 64 fs 32 fs MCS[2:0] 011 256 fs 128 fs 64fs 010 384 fs 192 fs 96 fs 001 512 fs 256 fs 128 fs 000 768 fs 384 fs 192 fs
Input sample rate fs (kHz)
5.1.2
Interpolation ratio select
Table 12.
Bit 4..3
Interpolation ratio select
RW RW RST 00 Name IR [1:0] Description Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency
The STA559BWQS has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 13. IR bit settings as a function of input sample rate
IR 00 00 00 01 01 10 10 1st stage interpolation ratio 2 times oversampling 2 times oversampling 2 times oversampling Pass-through Pass-through 2 times downsampling 2 times downsampling
Input sample rate fs (kHz) 32 44.1 48 88.2 96 176.4 192
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STA559BWQS
Register description
5.1.3
Thermal warning recovery bypass
Table 14.
Bit
Thermal warning recovery bypass
RW RST Name Description Thermal-warning recovery bypass: 0: Thermal warning recovery enabled 1: Thermal warning recovery disabled
5
RW
1
TWRB
If thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery will determine if the -3 dB output limit is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit will be removed and the gain will be added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit will remain until TWRB is changed to zero or the device is reset.
5.1.4
Thermal warning adjustment bypass
Table 15.
Bit
Thermal warning adjustment bypass
RW RST Name Description Thermal-warning adjustment bypass: 0: Thermal warning adjustment enabled 1: Thermal warning adjustment disabled
6
RW
1
TWAB
The on-chip STA559BWQS power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3 dB output limit (determined by TWOCL in Coeff RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.
5.1.5
Fault detect recovery bypass
Table 16.
Bit
Fault detect recovery bypass
RW RST Name Description Fault-detect recovery bypass: 0: Fault detect recovery enabled 1: Fault detect recovery disabled
7
RW
0
FDRB
The on-chip STA559BWQS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), hold it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (FDRC registers 0x29 - 0x2A), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1.
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Register description
STA559BWQS
5.2
Configuration register B (addr 0x01)
D7 C2IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0
5.2.1
Serial audio input interface format
Table 17.
Bit 0 1 2 3
Serial audio input interface format
RW RW RW RW RW RST 0 0 0 0 Name SAI0 SAI1 SAI2 SAI3 Serial audio input interface format: determines the interface format of the input serial digital audio interface. Description
5.2.2
Serial data interface
The STA559BWQS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA559BWQS always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 & 2 SDI12. The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (configuration register B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-First. Available formats are shown in the tables and figure that follow.
5.2.3
Serial data first bit
Table 18. Serial data first bit
SAIFB 0 1 MSB-first LSB-first Format
Table 19.
Support serial audio input formats for MSB-First (SAIFB = 0)
SAI [3:0] 0000 SAIFB 0 0 I2S 15 bit data Left/Right-justified 16 bit data Interface format
BICKI 32 fs
0001
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STA559BWQS Table 19.
Register description Support serial audio input formats for MSB-First (SAIFB = 0) (continued)
SAI [3:0] 0000 0001 0010 48 fs 0110 1010 1110 0000 0001 0010 64 fs 0110 1010 1110 0 0 0 Right-Justified 20 bit data Right-Justified 18 bit data Right-Justified 16 bit data 0 0 0 0 0 0 Right-Justified 20 bit data Right-Justified 18 bit data Right-Justified 16 bit data I2S 16-24 bit data Left-Justified 16-24 bit data Right-Justified 24 bit data SAIFB 0 0 0 I2 Interface format S 16-23 bit data
BICKI
Left-Justified 16-24 bit data Right-Justified 24 bit data
Table 20.
Supported serial audio input formats for LSB-First (SAIFB = 1)
SAI [3:0] 1100 SAIFB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I2S 15 bit data Interface format
BICKI 32 fs
1110 0100 0100 1000 1100 0001 0101 48 fs 1001 1101 0010 0110 1010 1110
Left/Right-Justified 16 bit data I2S 23 bit data I2S 20 bit data I2S 18 bit data LSB First I2S 16 bit data Left-Justified 24 bit data Left-Justified 20 bit data Left-Justified 18 bit data Left-Justified 16 bit data Right-Justified 24 bit data Right-Justified 20 bit data Right-Justified 18 bit data Right-Justified 16 bit data
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Register description Table 20.
STA559BWQS Supported serial audio input formats for LSB-First (SAIFB = 1) (continued)
SAI [3:0] 0000 0100 1000 1100 0001 0101 SAIFB 1 1 1 1 1 1 1 1 1 1 1 1 I S 24 bit data I2S 20 bit data I2S 18 bit data LSB first I2S 16 bit data Left-Justified 24 bit data Left-Justified 20 bit data Left-Justified 18 bit data Left-Justified 16 bit data Right-Justified 24 bit data Right-Justified 20 bit data Right-Justified 18 bit data Right-Justified 16 bit data
2
BICKI
Interface format
64 fs 1001 1101 0010 0110 1010 1110
5.2.4
Delay serial clock enable
Table 21.
Bit
Delay serial clock enable
RW RST Name Description Delay serial clock enable: 0: No serial clock delay 1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some IS master devices
5
RW
0
DSCKE
5.2.5
Channel input mapping
Table 22.
Bit 6 7
Channel input mapping
RW RW RW RST 0 1 Name C1IM C2IM Description 0: Processing channel 1 receives left I2S input 1: Processing channel 1 receives right I2S input 0: Processing channel 2 receives left I2S input 1: Processing channel 2 receives right I2S input
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel.
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STA559BWQS
Register description
5.3
Configuration register C (addr 0x02)
D7 OCRB 1 D6 D5 CSZ3 0 D4 CSZ2 1 D3 CSZ1 0 D2 CSZ0 1 D1 OM1 1 D0 OM0 1
5.3.1
DDX power output mode
Table 23.
Bit 0 1
DXX power output mode
RW RW RW RST 1 1 Name OM0 OM1 Description DDX power output mode: selects configuration of DDX output.
The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 24. Output modes
Output stage - Mode Drop compensation Discrete output stage - Tapered compensation Full power mode Variable drop compensation (CSZx bits)
OM[1,0] 00 01 10 11
5.3.2
DDX compensating pulse size register
Table 25.
Bit 2 3 4 5
DXX compensating pulse size register
RW RW RW RW RW RST 1 0 1 0 Name CSZ0 CSZ1 CSZ2 CSZ3 Contra size register: when OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 15 clock periods. Description
Table 26.
Compensating pulse size
Compensating pulse size 0ns (0 tick) Compensating pulse size 20ns (1 tick) Clock period compensating pulse size ... 300 ns (15 tick) Clock period compensating pulse size
CSZ[3:0] 0000 0001 ... 1111
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Register description
STA559BWQS
5.3.3
Over-current warning detect adjustment bypass
Table 27.
Bit
Over-current warning detect adjustment bypass
RW RST Name Description Over-current warning adjustment bypass: 0: Over-current warning adjustment enabled 1: Over-current warning adjustment disabled
7
RW
1
OCRB
The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control block will force a adjustment to the modulation limit (default -3 dB) in an attempt to eliminate the over-current warning condition. Once the overcurrent warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (Thermal Warning/Over Current Limit) setting which is address 0 x 37 of the user defined coefficient RAM.
5.4
Configuration register D (addr 0x03)
D7 MME 0 D6 ZDE 1 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0
5.4.1
High-pass filter bypass
Table 28.
Bit 0
High-pass filter bypass
RW RW RST 0 Name HPB Description High-pass filter bypass bit. setting of one bypasses internal AC coupling digital high-pass filter.
The STA559BWQS features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.
5.4.2
De-emphasis
Table 29.
Bit
De-emphasis
RW RST Name De-emphasis: 0: No de-emphasis 1: De-emphasis Description
1
RW
0
DEMP
Setting the DEMP bit enables de-emphasis on all channels
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STA559BWQS
Register description
5.4.3
DSP bypass
Table 30.
Bit
DSP bypass
RW RST Name Description DSP bypass bit: 0: Normal operation 1: Bypass of biquad and bass/treble functionality
2
RW
0
DSPB
Setting the DSPB bit bypasses the EQ functionality of the STA559BWQS.
5.4.4
Post-scale link
Table 31.
Bit
Post-scale link
RW RST Name Description Post-scale link: 0: Each channel uses individual post-scale value 1: Each channel uses channel 1 post-scale value
3
RW
0
PSL
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster.
5.4.5
Biquad coefficient link
Table 32.
Bit
Biquad coefficient link
RW RST Name Description Biquad link: 0: Each channel uses coefficient values 1: Each channel uses channel 1 coefficient values
4
RW
0
BQL
For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
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Register description
STA559BWQS
5.4.6
Dynamic range compression/anti-clipping bit
Table 33.
Bit
Dynamic range compression/anti-clipping bit
RW RST Name Description Dynamic range compression/anti-clipping 0: Limiters act in anti-clipping mode 1: Limiters act in dynamic range compression mode
5
RW
0
DRC
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
5.4.7
Zero-detect mute enable
Table 34.
Bit 6
Zero-detect mute enable
RW RW RST 1 Name ZDE Description Zero-detect mute enable: setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.
5.4.8
MiamiMode enable
Table 35.
Bit
MiamiMode enable
RW RST Name Description Miami-Mode enable: 0: Sub mix into left/right disabled 1: Sub mix into left/right enabled
7
RW
0
MME
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STA559BWQS
Register description
5.5
Configuration register E (addr 0x04)
D7 SVE 1 D6 ZCE 1 D5 DCCV 0 D4 PWMS 0 D3 AME 0 D2 NSBW 0 D1 MPC 1 D0 MPCV 0
5.5.1
Max power correction variable
Table 36.
Bit
Max power correction variable
RW RST Name Description Max power correction variable: 0: Use standard MPC coefficient 1: Use MPCC bits for MPC coefficient
0
RW
0
MPCV
5.5.2
Max power correction
Table 37.
Bit 1
Max power correction
RW RW RST 1 Name MPC Description Max power correction: setting of 1 enables power bridge correction for THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD + N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the lineout channels.
5.5.3
Noise-shaper bandwidth selection
Table 38.
Bit RW
Noise-shaper bandwidth selection
RST Name Description Noise-shaper bandwidth selection: 1 - 3rd order NS 0 - 4th order NS
2
RW
0
NSBW
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Register description
STA559BWQS
5.5.4
AM mode enable
Table 39.
Bit RW
AM mode enable
RST Name Description AM mode enable: 0 - Normal DDX operation. 1 - AM reduction mode DDX operation
3
RW
0
AME
STA559BWQS features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio.
5.5.5
PWM speed mode
Table 40.
Bit RW
PWM speed mode
RST Name Description PWM speed selection: 0 - Normal speed (384 kHz) all channels 1 - Odd speed (341.3k Hz) all channels
4
RW
0
PWMS
5.5.6
Distortion compensation variable enable
Table 41.
Bit RW
Distortion compensation variable enable
RST Name Description Distortion compensation variable enable: 0 - Uses preset DC coefficient. 1 - Uses DCC coefficient.
5
RW
0
DCCV
5.5.7
Zero-crossing volume enable
Table 42.
Bit RW
Zero-crossing volume enable
RST Name Description Zero-crossing volume enable: 1 - Volume adjustments will only occur at digital zerocrossings 0 - Volume adjustments will occur immediately
6
RW
1
ZCE
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible.
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STA559BWQS
Register description
5.5.8
Soft volume update enable
Table 43.
Bit RW
Soft volume update enable
RST Name Description Soft volume enable: 1: Volume adjustments ramp according to SVR settings 0: Volume adjustments will occur immediately
7
RW
1
SVE
5.6
Configuration register F (addr 0x05)
D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 LDTE 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1 0 D0 OCFG0 0
5.6.1
Output configuration
Table 44.
Bit 0 1
Output configuration
RW RW RW RST 0 0 Name OCFG0 Selects the output configuration OCFG1 Description
Table 45.
OCFG[1:0]
Output configuration engine selection
Output configuration 2 channel (full-bridge) power, 2 channel data-out: 1A/1B 1A/1B 2A/2B 2A/2B LineOut1 3A/3B LineOut2 4A/4B Line out configuration determined by LOC register 2 (half-bridge). 1 (full-bridge) on-board power: 1A 1A Binary 0 2A 1B Binary 90 3A/3B 2A/2B Binary 45 1A/B 3A/B Binary 0 2A/B 4A/B Binary 90 2 channel (full-bridge) power, 1 channel DDX: 1A/1B 1A/1B 2A/2B 2A/2B 3A/3B 3A/3B EAPDEXT and TWARNEXT active Config pin
00
0
01
0
10
0
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Register description Note:
STA559BWQS To the left of the arrow is the processing channel. Note that though the defaults are shown, using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs Figure 30. OCFG = 01
Figure 29. OCFG = 00 (default value)
Half Bridge
OUT1A
Channel 1
Half Bridge
Half Bridge
Channel 1
OUT1A
OUT1B OUT2A
Half Bridge
Half Bridge
Channel 2
OUT1B OUT2A
Channel 2
Half Bridge
Half Bridge
OUT2B
Channel 3
OUT3A OUT3B LPF
LineOut 1
Half Bridge
OUT2B
OUT4A OUT4B LPF
LineOut 2
Figure 31. OCFG = 10
Half Bridge
OUT1A
Channel 1
Half Bridge
OUT1B OUT2A
Half Bridge
Channel 2
Half Bridge
OUT2B
OUT3A OUT3B EAPD Power Device Channel 3
5.6.2
Invalid input detect mute enable
Table 46.
Bit 2
Invalid input detect mute enable
RW RW RST 1 Name IDE Description Invalid input detect mute enable: setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid.
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STA559BWQS
Register description
5.6.3
Binary output mode clock loss detection
Table 47.
Bit 3
Binary output mode clock loss detection
RW RW RST 1 Name BCLE Description Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
5.6.4
LRCK double trigger protection
Table 48.
Bit 4
LRCK double trigger protection
RW RW RST 1 Name LDTE Description LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
5.6.5
Auto EAPD on clock loss
Table 49.
Bit 5
Auto EAPD on clock loss
RW RW RST 0 Name ECLE Description Auto EAPD on clock loss
When active, will issue a power device power down signal (EAPD) on clock loss detection.
5.6.6
IC power down
Table 50.
Bit
IC power down
RW RST Name Description IC power down: 0 - IC powerdown low-power condition 1 - IC normal operation
7
RW
1
PWDN
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block will be gated. This places the IC in a very low power consumption state.
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Register description
STA559BWQS
5.6.7
External amplifier power down
Table 51.
Bit
External amplifier power down
RW RST Name Description External amplifier power down: 0: External power stage power down active 1: Normal operation
7
RW
0
EAPD
The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register will also control the DDX4B/EAPD output pin when OCFG = 10.
5.7
5.7.1
Volume control registers (addr 0x06 - 0x0A)
Mute/line output configuration register
D7 LOC1 0 D6 LOC0 0 D5 D4 D3 C3M 0 D2 C2M 0 D1 C1M 0 D0 MMUTE 0
Table 52.
Line output configuration
Line output configuration Line output fixed - no volume, no EQ Line output variable - CH3 volume effects line output, no EQ Line output variable with EQ - CH3 volume effects line output
LOC[1:0] 00 01 10
Line output is only active when OCFG = 00. In this case LOC will determine the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
5.7.2
Master volume register
D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1
5.7.3
Channel 1 volume
D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0
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STA559BWQS
Register description
5.7.4
Channel 2 volume
D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0
5.7.5
Channel 3/line output volume
D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0
The volume structure of the STA559BWQS consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5dB steps from +48 dB to 80 dB. As an example if C3V = 00h or +48 dB and MV = 18h or -12 dB, then the total gain for channel 3 = +36 dB. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (CxM) will mute only that channel. Both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -80 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates will occur immediately. Table 53. Master volume offset as a function of MV[7:0]
MV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01001100 (0x4C) ... 11111110 (0xFE) 11111111 (0xFF) Volume offset from channel value 0 dB -0.5 dB -1 dB ... -38 dB ... -127.5 dB Hard master mute
Table 54.
Channel volume as a function of CxV[7:0]
CxV[7:0] Volume +48 dB +47.5 dB
00000000 (0x00) 00000001 (0x01)
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Register description Table 54. Channel volume as a function of CxV[7:0]
CxV[7:0] 00000010 (0x02) ... 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) ... 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) ... 11101100 (0xEC) 11101101 (0xED) ... 11111111 (0xFF) Volume +47 dB ... +0.5 dB 0 dB -0.5 dB ... -59.5 dB -60 dB -61 dB -62 dB ... -80 dB Hard channel mute ... Hard channel mute
STA559BWQS
5.8
5.8.1
Auto mode registers (addr 0x0B and 0x0C)
AutoMode register 1 (addr 0x0B)
D7 D6 D5 AMGC1 0 D4 AMGC2 0 D3 D2 D1 D0
Table 55.
AutoMode gain compression/limiters selection
Mode User programmable GC AC no clipping 2.1 AC limited clipping (10%) 2.1 DRC nighttime listening mode 2.1
AMGC[1:0] 00 01 10 11
5.8.2
AutoMode register 2 (addr 0x0C)
D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0
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STA559BWQS
Register description
5.8.3
AM interference frequency switching
Table 56.
Bit
AM interference frequency switching
RW RST Name Description AutoMode AM enable 0: Switching frequency determined by PWMS setting 1: Switching frequency determined by AMAM settings
0
RW
0
AMAME
Table 57.
AutoMode AM switching frequency selection
48 kHz/96 kHz Input Fs 0.535 MHz - 0.720 MHz 0.721 MHz - 0.900 MHz 0.901 MHz - 1.100 MHz 1.101 MHz - 1.300 MHz 1.301 MHz - 1.480 MHz 1.481 MHz - 1.600 MHz 1.601 MHz - 1.700 MHz 44.1 kHz/88.2 kHz Input Fs 0.535 MHz - 0.670 Mhz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz
AMAM[2:0] 000 001 010 011 100 101 110
5.8.4
Bass management crossover
Table 58.
Bit 4 5 6 7
Bass management crossover
RW RW RW RW RW RST 0 0 0 0 Name XO0 XO1 XO2 XO3 Selects the bass-management crossover frequency. A 1st-order hi-pass filter (channels 1 and 2) or a 2nd-order lo-pass filter (channel 3) at the selected frequency is performed. Description
Table 59.
Bass management crossover frequency
Crossover Frequency User-Defined 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz
XO[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
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Register description Table 59. Bass management crossover frequency
Crossover Frequency 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz
STA559BWQS
XO[3:0] 1010 1011 1100 1101 1110 1111
5.9
Channel configuration registers (addr 0x0E - 0x10)
D7 C1OM1 0 D7 C2OM1 0 D7 C3OM1 1 D6 C1OM0 0 D6 C2OM0 1 D6 C3OM0 0 D5 C1LS1 0 D5 C2LS1 0 D5 C3LS1 0 D4 C1LS0 0 D4 C2LS0 0 D4 C3LS0 0 D3 C1BO 0 D3 C2BO 0 D3 C3BO 0 D2 C1VPB 0 D2 C2VPB 0 D2 C3VPB 0 D1 C1EQBP 0 D1 C2EQBP 0 D1 D0 C1TCB 0 D0 C2TCB 0 D0
5.9.1
Tone control bypass
Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. CxTCB: 0 - Perform tone control on channel X - normal operation 1 - Bypass tone control on channel X
5.9.2
EQ bypass
EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. CxEQBP: 0 - Perform EQ on channel X - normal operation 1 - Bypass EQ on channel X
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STA559BWQS
Register description
5.9.3
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
5.9.4
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel will be considered the positive output and output B is negative inverse. CxBO: 0 - DDX tri-state output - normal operation 1 - Binary output.
5.9.5
Limiter select
Limiter selection can be made on a per-channel basis according to the channel limiter select bits. Table 60.
.
Channel limiter mapping as a function of CxLS bits
Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2
CxLS[1,0] 00 01 10
5.9.6
Output mapping
Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. Table 61.
.
Channel output mapping as a function of CxOM bits
Channel x output source from Channel 1 Channel 2 Channel 3 00 01 10
CxOM[1,0]
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Register description
STA559BWQS
5.10
5.10.1
Tone control register (addr 0x11)
Tone control
D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1
Table 62.
Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 Boost/cut -12 dB -12 dB ... -4 dB -2 dB 0 dB +2 dB +4 dB ... +12 dB +12 dB +12 dB
5.11
5.11.1
Dynamics control registers (addr 0x12 - 0x15)
Limiter 1 attack/release rate
D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0
5.11.2
Limiter 1 attack/release threshold
D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1
5.11.3
Limiter 2 attack/release rate
D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0
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STA559BWQS
Register description
5.11.4
Limiter 2 attack/release threshold
D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1
The STA559BWQS includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in configuration register F, bit 0 address 0x05. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA559BWQS it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 32. Basic limiter and volume flow diagram.
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Register description
STA559BWQS
Table 63.
LxA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Limiter attack rate as a function of LxA bits.
Attack rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Slow Fast
Table 64.
LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Limiter release rate as a function of LxR bits.
Release rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Slow Fast
Anti-clipping mode
Table 65. Limiter attack threshold as a function of LxAT bits (AC-Mode)
AC (dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10
Table 66.
Limiter release threshold as a function of LxRT bits (ACMode)
AC (dB relative to FS) - -29 dB -20 dB -16 dB -14 dB -12 dB -10 dB -8 dB -7 dB -6 dB -5 dB -4 dB -3 dB -2 dB -1 dB -0 dB
LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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STA559BWQS
Register description
Dynamic range compression mode
Table 67. Limiter attack threshold as a function of LxAT bits (DRCmode).
DRC (dB relative to volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4
Table 68.
Limiter release threshold as a as a function of LxRT bits (DRC-mode).
DRC (db relative to volume + LxAT) - -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB -9 dB -6 dB
LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LxRT [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
5.12
5.12.1
User-defined coefficient control registers (addr 0x16 - 0x26)
Coefficient address register
D7 D6 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0
5.12.2
Coefficient b1data register bits 23..16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
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Register description
STA559BWQS
5.12.3
Coefficient b1data register bits 15..8 address
D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0
5.12.4
Coefficient b1data register bits 7..0
D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0
5.12.5
Coefficient b2 data register bits 23..16
D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0
5.12.6
Coefficient b2 data register bits 15..8
D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0
5.12.7
Coefficient b2 data register bits 7..0
D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0
5.12.8
Coefficient a1 data register bits 23..16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
5.12.9
Coefficient a1 data register bits 15..8
D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0
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STA559BWQS
Register description
5.12.10
Coefficient a1 data register bits 7..0
D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0
5.12.11
Coefficient a2 data register bits 23..16
D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0
5.12.12
Coefficient a2 data register bits 15..8
D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0
5.12.13
Coefficient a2 data register bits 7..0
D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0
5.12.14
Coefficient b0 data register bits 23..16
D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0
5.12.15
Coefficient b0 data register bits 15..8
D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0
5.12.16
Coefficient b0 Data Register Bits 7..0
D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0
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Register description
STA559BWQS
5.12.17
Coefficient write/read control register
D7 D6 D5 D4 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA559BWQS via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of IC registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM. The following are instructions for reading and writing coefficients. Reading a coefficient from RAM
" " " " "
write 6-bits of address to I2C register 0x16 write 1 to R1 bit in I2C address 0x26 read top 8-bits of coefficient in I2C address 0x17 read middle 8-bits of coefficient in I2C address 0x18 read bottom 8-bits of coefficient in I2C address 0x19. write 6-bits of address to I2C register 0x16 write 1 to RA bit in I2C address 0x26 read top 8-bits of coefficient in I2C address 0x17 read middle 8-bits of coefficient in I2C address 0x18 read bottom 8-bits of coefficient in I2C address 0x19 read top 8-bits of coefficient b2 in I2C address 0x1A read middle 8-bits of coefficient b2 in I2C address 0x1B read bottom 8-bits of coefficient b2 in I2C address 0x1C read top 8-bits of coefficient a1 in I2C address 0x1D read middle 8-bits of coefficient a1 in I2C address 0x1E read bottom 8-bits of coefficient a1 in I2C address 0x1F read top 8-bits of coefficient a2 in I2C address 0x20 read middle 8-bits of coefficient a2 in I2C address 0x21 read bottom 8-bits of coefficient a2 in I2C address 0x22 read top 8-bits of coefficient b0 in I2C address 0x23 read middle 8-bits of coefficient b0 in I2C address 0x24 read bottom 8-bits of coefficient b0 in I2C address 0x25.
Reading a set of coefficients from RAM
" " " " " " " " " " " " " " " " "
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STA559BWQS Writing a single coefficient to RAM
" " " " "
Register description
write 6-bits of address to I2C register 0x16 write top 8-bits of coefficient in I2C address 0x17 write middle 8-bits of coefficient in I2C address 0x18 write bottom 8-bits of coefficient in I2C address 0x19 write 1 to W1 bit in I2C address 0x26. write 6-bits of starting address to I2C register 0x16 write top 8-bits of coefficient b1 in I2C address 0x17 write middle 8-bits of coefficient b1 in I2C address 0x18 write bottom 8-bits of coefficient b1 in I2C address 0x19 write top 8-bits of coefficient b2 in I2C address 0x1A write middle 8-bits of coefficient b2 in I2C address 0x1B write bottom 8-bits of coefficient b2 in I2C address 0x1C write top 8-bits of coefficient a1 in I2C address 0x1D write middle 8-bits of coefficient a1 in I2C address 0x1E write bottom 8-bits of coefficient a1 in I2C address 0x1F write top 8-bits of coefficient a2 in I2C address 0x20 write middle 8-bits of coefficient a2 in I2C address 0x21 write bottom 8-bits of coefficient a2 in I2C address 0x22 write top 8-bits of coefficient b0 in I2C address 0x23 write middle 8-bits of coefficient b0 in I2C address 0x24 write bottom 8-bits of coefficient b0 in I2C address 0x25 write 1 to WA bit in I2C address 0x26.
Writing a set of coefficients to RAM
" " " " " " " " " " " " " " " " "
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address would specify the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA559BWQS will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data.
5.12.18
User-defined EQ
The STA559BWQS provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808).
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Register description
STA559BWQS
Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 where x represents the channel and the y the biquad number. For example C2H41 is the b2 coefficient in the fourth biquad for channel 2. Additionally, the STA559BWQS allows specification of a high-pass filter (processing channels 1 and 2) and a lo-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are 2nd order filters that use the biquad equation noted above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in the table below. By default, all user-defined filters are pass-thru where all coefficients are set to 0, except the b0/2 coefficient which is set to 0x400000 (representing 0.5)
5.12.19
Pre-scale
The STA559BWQS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All channels can use the channel 1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
5.12.20
Post-scale
The STA559BWQS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 post-scale factor by setting the postscale link bit. By default, all post-scale factors are set to 0x7FFFFF. When Line output is being utilized, channel 3 post-scale will affect both channels 3 and 4.
5.12.21
Over-current post-scale
The STA559BWQS provides a simple mechanism for reacting to over-current detection in the power-block. When the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted. The amount of attenuation to be applied in this situation can be adjusted by modifying the Over-current Post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the over-current post-scale factor is set to 0x5A9DF7. Once the over-current attenuation is applied, it remains until the device is reset.
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STA559BWQS Table 69.
0 1 2 3 4 5 ... 19 20 21 ... 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Register description RAM block for biquads, mixing, scaling, and bass management
Coefficient C1H10(b1/2) C1H11(b2) Channel 1 - Biquad 1 C1H12(a1/2) C1H13(a2) C1H14(b0/2) Channel 1 - Biquad 2 ... Channel 1 - Biquad 4 Channel 2 - Biquad 1 ... Channel 2 - Biquad 4 C1H20 ... C1H44 C2H10 C2H11 ... C2H44 C12H0(b1/2) High-pass 2nd order filter for XO = 000 C12H1(b2) C12H2(a1/2) C12H3(a2) C12H4(b0/2) C3H0(b1/2) Low-pass 2nd order filter for XO = 000 C3H1(b2) C3H2(a1/2) C3H3(a2) C3H4(b0/2) Channel 1 - Pre-scale Channel 2 - Pre-scale Channel 1 - Post-scale Channel 2 - Post-scale Channel 3 - Post-scale TWARN/OC- Limit Channel 1 - Mix 1 Channel 1 - Mix 2 Channel 2 - Mix 1 Channel 2 - Mix 2 Channel 3 - Mix 1 Channel 3 - Mix 2 UNUSED UNUSED C1PreS C2PreS C1PstS C2PstS C3PstS TWOCL C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 ... 0x400000 0x000000 0x000000 ... 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x5A9DF7 0x7FFFFF 0x000000 0x000000 0x7FFFFF 0x400000 0x400000 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x13 0x14 0x15 ... 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
Index (Decimal) Index (Hex)
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Register description
STA559BWQS
5.13
Variable max power correction registers (addr 0x27 - 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
D7 MPCC15 0 D7 MPCC7 1 D6 MPCC14 0 D6 MPCC6 1 D5 MPCC13 0 D5 MPCC5 0 D4 MPCC12 1 D4 MPCC4 0 D3 MPCC3 0 D3 MPCC11 1 D2 MPCC2 0 D2 MPCC10 0 D1 MPCC1 0 D1 MPCC9 1 D0 MPCC8 0 D0 MPCC0 0
5.14
Variable distortion compensation registers (addr 0x29-0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
D7 DCC15 1 D7 DCC7 0 D6 DCC14 1 D6 DCC6 0 D5 DCC13 1 D5 DCC5 1 D4 DCC12 1 D4 DCC4 1 D3 DCC3 0 D3 DCC11 0 D2 DCC2 0 D2 DCC10 0 D1 DCC1 1 D1 DCC9 1 D0 DCC8 1 D0 DCC0 1
5.15
Fault detect recovery constant registers (addr 0x2B - 0x2C)
FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE output will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 0.1 ms.
D7 FDRC15 0 D7 FDRC7 0 D6 FDRC14 0 D6 FDRC6 0 D5 FDRC13 0 D5 FDRC5 0 D4 FDRC12 0 D4 FDRC4 0 D3 FDRC3 1 D3 FDRC11 0 D2 FDRC2 1 D2 FDRC10 0 D1 FDRC1 0 D1 FDRC9 0 D0 FDRC8 0 D0 FDRC0 0
5.16
Device status register (addr 0x2D)
D7 PLLUL D6 FAULT D5 UVFAULT D4 OVFAULT D3 OCFAULT D2 OCWARN D1 TFAULT D0 TWARN
This read-only register provides fault and thermal-warning status information from the power control block.
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STA559BWQS
Application
6
6.1
Application
Application scheme for power supplies
Figure 33 below shows a circuit diagram of a typical application for STA559BWQS.Particular care has to be given to the layout of the PCB, especially the power supplies. The 3.3- resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation on the digital portion of the device due to inductive tracks of the PCB. This same rule also applies to all the decoupling capacitors in order to limit any kind of spikes on the supplies. Figure 33. Application schematic
3R3 1 2 3 4 100nF 1uF 35V OUT2B 5 6 7 8 100nF 100nF OUT2A VCC OUT1B 9 10 11 12 1uF 35V OUT1A 100nF 13 14 15 16 DDX3B DDX3A 17 18 1000uF 35V + GND_SUB SA TEST_MODE VSS VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD
GND CONFIG
VDD_DIG GND_DIG SCL SDA INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG TWARN/4A EAPD/4B
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 3R3 TW EAPD PLL_FILT DATA SCL SDA INTL
3V3 100nF 3V3
GND_DIG
10K
RESET 1nF RESET
LRCKI BICKI XTI
BEAD GND_DIG
100nF
BEAD
PLL_GND
GND_DIG
3V3
PWDN 100nF
GND_DIG
3V3
DDX3B DDX3A
6.2
PLL filter schematic
It is recommended to use the below schematic and values in Figure 34 below for the PLL loop filter. In order to achieve the best performance from the device in general applications the filter ground (PLL_GND) must be connected as close as possible to the device pin PLL_GND. Concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. Figure 34. PLL application schematic
FILTER_PLL
2K2 680pF
Component leads must be kept as short as possible
4.7nF
BEAD
100pF
GND_DIG
PLL_GND
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Application
STA559BWQS
6.3
Typical output configuration
Figure 35 shows the typical output configuration used for BTL stereo mode. Please refer to the application note for other recommended output configuration schematics. Figure 35. Output configuration for stereo BTL mode
22uH OUT1A 100nF
6.2 22
100nF 470nF 100nF LEFT
330pF
6.2
100nF OUT1B 22uH
22uH OUT2A 100nF
6.2 22
100nF 470nF 100nF RIGHT
330pF
6.2
100nF OUT2B 22uH
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STA559BWQS
Package thermal characteristics
7
Package thermal characteristics
Due to the high efficiency of the system the dissipated power is negligible, allowing the use of the STA559BWQS without heat sink but using only a small copper area on the PCB. Using a double layer PCB the thermal resistance junction to ambient with two copper ground areas of 3 x 3 cm2 and with 16 via holes (see Figure 36) is 24 C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA559BWQS is: 2 x 3 W into 4 at 5 V 2 x 0.7 W + 1 x 3 W into 4 at 5 V 2 x 1.4 W + 1 x 6 W into 2 at 5 V Pd max ~ 600mW Pd max < 500mW Pd max ~ 800mW
This gives, with the suggested board copper area, a max Tj of only approximately 20 C for the worst case of the above mentioned applications. The safety margin before the thermal protection intervention (Tj=150C) is thus ensured, also in severe environments where the ambient temperature exceeds 50 C. Figure 36. Double layer PCB with copper ground area and with 16 via holes
Figure 37 shows the power derating curves for the PowerSSO-36 package on a board with two different sizes of copper layers. Figure 37. PowerSSO-36 power derating curve
Pd (W)
8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 140 160
Tamb ( C)
Copper Area 2x2 cm and via holes Copper Area 3x3 cm and via holes
STA559BWQS STA335BW PSSO36 PowerSSO-36
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Package information
STA559BWQS
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 38. PowerSSO-36 (slug-up) mechanical data and package dimensions
DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h k L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.5 8.5 2.3 0.10 0.06 10.50 0.40 5 0.55 4.3 10 1.2 0.8 2.9 3.65 1.0 4.1 6.5 4.7 7.3 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.287 0.90 0.022 0.169 10 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.019 0.335 0.090 0.004 0.002 0.413 0.016 5 0.035 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
OUTLINE AND MECHANICAL DATA
10.10
0.398
PowerSSO-36 (slug-down)
(1) "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006")
A2
A
hx45u
G
LEAD COPLANARITY
A
D
e
stand-off
a1
T
Y M
Gauge plane 0.25
L
O
E
H
F
U
B
0.1 M A B
b e3
S
BOTTOM VIEW
X
7587131 A
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k
c
Q
STA559BWQS
License information
9
License information
Supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready to use final product. An independent license for such use is required and can be obtained by contacting the company or companies concerned. Once the license is obtained, a copy must be sent to STMicroelectronics. The details of all the features requiring licenses are not provided within the datasheet and register manual. They are provided only after a copy of the license has been received by STMicroelectronics. The feature requiring license is:
QXpander (QHD(R))
QHD(R) and QXpander(R) are intellectual property of QSounds Lab Inc. A license can be obtained with the STA559BWQS via STMicroelectronics, please contact the HPC Audio Division Product Manager for details. Alternatively the license can be obtained directly from QSound Labs Inc. For details please contact: sales@qsound.com or QSound Labs, Inc 400 - 3115 12th Street NE Calgary, AB Canada T2E 7J2
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Trademarks and other acknowledgements
STA559BWQS
10
Trademarks and other acknowledgements
DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. QHD and QXpander are registered trademarks of QSound Labs Inc.
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STA559BWQS
Revision history
11
Revision history
Table 70.
Date 28-Mar-2008
Document revision history
Revision 1 Initial release. Changes
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STA559BWQS
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